As electrically programmable nonvolatile semiconductor memory devices, the EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used for storing programs or data. Particularly, in recent years, such EEPROMs used as data storage devices have come to meet a great demand, for example, they are used in IC cards. Generally, as such data storage EEPROMs, not flash EEPROMs, in which several kilobytes to several tens of kilobytes of information are erased simultaneously, but byte-programmable EEPROMs that can erase/program information in bytes are used. The number of erase/program cycles required in data storage devices is usually over 100,000 times, which is more than that in program storage devices. If an EEPROM is mounted together with a microcomputer on the same chip, it can prevent data reading from external.
However, the byte programmable EEPROM used for storing data is often confronted with a problem of disturbance which occurs in unselected memory cells during programming/erasing operation. The disturbance mentioned here means a phenomenon that a voltage to be applied to a selected memory cell also comes to be applied to unselected memory cells connected to the same line, thereby information is programmed/erased weakly in/from the unselected memory cells and data is lost gradually therefrom. In a flash EEPROM, when erasing is performed simultaneously on a block of memory cells which are connected to the same line as that of a line to which a high voltage is applied to program/erase, a disturbance occurring during erasing does not become a problem at all and memory cells receive a disturbance only during one-time programming. On the other hand, in the byte programming type EEPROM in the worst case, no programming/erasing is done in/from some memory cells while all other bytes in the same block are programmed/erased 100,000 times. Each of those memory cells will receive disturbances as many as 100,000 times x (the number of bytes in the block—1). The byte programming type EEPROM comes to have disturbance conditions far more strict than those of the flash EEPROM.
The non-patent document 1 discloses a technique for realizing programming/erasing cycles of 100,000 times in the byte programming type EEPROM. FIG. 1 shows a cross sectional view of memory cells of such an EEPROM. FIG. 2 shows a circuit diagram of a memory cell array. As shown in FIG. 1, one memory cell consists of an MNOS type memory for storing information by accumulating a charge in a silicon nitride film SIN and a select transistor for selecting the cell for reading. In the memory cell array, as shown in FIG. 2, select gate lines (word lines) SG0 to SGn for connecting select gate electrodes SG and memory gate lines MG0 to MGn for connecting memory gates MG are extended in parallel to each other while bit lines BL0 to BL7 for connecting drain regions D and source lines SL to SL7 for connecting source regions S of memory cells respectively are extended in a direction orthogonal to the word lines. And, wells WELL1 to WELLn of memory cells are divided to correspond to memory cells connected to word lines and grouped in 8 bits. Information is programmed/erased in units of 8 bits connected to a common memory gate line and a well, that is, in byte units. FIG. 3 shows voltage conditions for erasing/programming a block of selected memory cells shown in FIG. 2. In those selected memory cells in/from which information is to be erased/programmed, a high voltage is applied between a memory gate MG and a well WELL to erase information from an object memory cell by means of tunneling of holes through a bottom oxide film BOTOX and program information in the memory cell by means of tunneling of electrons. In an unselected memory cell, the same voltage as that applied to the memory gate MG is applied to the well WELL or source line SL so as not to apply an electric field in the gate insulation film of the NMOS memory. In other words, according to the above known technique, a well WELL is divided into single-byte regions so that no electric field is applied to the gate insulation film of the MNOS memory of any unselected memory cell during programming/erasing, thereby data is held in the memory cell even when reprogramming is done more than 100,000 times under no influence of a disturbance.
In the above byte programming type EEPROM, in each memory cell connected to a selected memory gate line MG and an unselected well WELL, the same voltage is applied to both of the memory gate MG and the well WELL. At that time, however, a high electric field is applied to between the memory gate MG and the source S, thereby electrons and holes will be injected into an adjacent silicon nitride film SIN of the source shown in FIG. 1. If the length of the memory gate Lmg is large, the charge in the silicon nitride film SIN is held in the center of the channel of the MNOS memory away from the source S, so that the charge injection around the source S arises no problem. However, if the length of the memory gate Lmg is small, the charge injection around the source comes to lose the resistance to the disturbance during programming/erasing, thereby the programming/erasing cycles of 100,000 times cannot be assured any more. In other words, the above conventional technique is just effective for the byte programming type EEPROM limited in the shrinkage in memory cell size.
Furthermore, according to the above conventional technique, because programming/erasing is made by means of tunneling of electrons/holes, the technique is confronted with the following problems. (1) It takes much time to write/erase information. (2) The bottom oxide film BOTOX cannot be formed thicker, so that it is difficult to hold data at high temperatures over 100° C.
The patent document 1 discloses a nonvolatile memory in/from which information is programmed/erased by means of hot carrier injection, not by means of tunneling of electrons/holes as described above. FIG. 4 shows a cross sectional view of a memory cell of this memory. The memory is a split gate type MONOS memory having two gates (a select gate SG and a memory gate MG). In the memory, the memory gate insulation film consists of a top oxide film TOPOX, a silicon nitride film SIN, and a bottom oxide film BOTOX. Hot electrons are injected into the silicon nitride film SIN with a source-side injection method to program information while hot holes generated by BTBT (Band-To-Band Tunneling) are injected into the same film to erase information. This hot carrier injection can speedup both programming and erasing, as well as improve the data holding reliability compared to the tunneling injection.
In the case of the programming/erasing method by means of hot carrier injection described above, however, a high voltage is required to be applied to both source region S and memory gate MG, so that how to secure the resistance to disturbance during programming/erasing arises as a problem. And, in order to avoid applying of a high voltage to unselected memory cells during programming/erasing so as not to cause a disturbance in those memory cells, it is required to divide the memory gate line connected to the memory gate MG and the source line connected to the source region S into some single-byte portions. To realize such dividing, a high dielectric MOS transistor is required to select a memory gate line and a source line for each byte respectively. The area per memory cell including that of the MOS transistors thus becomes a double compared to that required when the both lines are not divided.
[Patent document 1] U.S. Pat. No. 5,969,383
[Patent document 2] Official gazette of JP-A No. 215584/1994 (corresponding U.S. Pat. No. 6,160,738)
[Non-patent document 1] IEICE TRANSACTION ON ELECTRONICS, 2001, Vol. E84-C, pp. 713-723